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NB4L16M 2.5V/3.3V, 5 Gb/s Multi Level Clock/Data Input to CML Driver / Receiver / Buffer/ Translator with Internal Termination
Description
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16 1
The NB4L16M is a differential driver/receiver/buffer/translator which can accept LVPECL, LVDS, CML, HSTL, LVCMOS/LVTTL and produce 400 mV CML output. The device is capable of receiving, buffering, and translating a clock or data signal that is as small as 75 mV operating up to 3.5 GHz or 5.0 Gb/s, respectively. As such, it is ideal for SONET, GigE, Fiber Channel and backplane applications (see Table 6 and Figures 20, 21 22, and 23). Differential inputs incorporate internal 50 W termination resistors and accept LVPECL (Positive ECL), LVTTL/LVCMOS, CML, HSTL or LVDS. The differential 16 mA CML output provides matching internal 50 W termination, and 400 mV output swing when externally receiver terminated, 50 W to VCC (see Figure 19). These features provide transmission line termination on chip, at the receiver and driver end, eliminating any use of additional external components. The VBB, an internally generated voltage supply, is available to this device only. For single-ended input configuration, the unused complementary differential input is connected to VBB as a switching reference voltage. The VBB reference output can be used also to re-bias capacitor coupled differential or single-ended output signals. For the capacitor coupled input signals, VBB should be connected to the VTD pin and bypassed to ground with a 0.01 mF capacitor. When not used VBB should be left open. This device is housed in a 3x3 mm 16 pin QFN package. Application notes, models, and support documentation are available at www.onsemi.com.
Features
1 QFN-16 MN SUFFIX CASE 485G A L Y W G
NB4L 16M ALYWG G = Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package
(Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D.
VCC VTD 50 W D D 50 W VTD VEE R2 R1 R1 R2 Q Q
* * * * * * * * * * *
Maximum Input Clock Frequency up to 3.5 GHz Maximum Input Data Rate up to 5.0 Gb/s < 0.7 ps Maximum Clock RMS Jitter < 10 ps Maximum Data Dependent Jitter at 2.5 Gb/s 220 ps Typical Propagation Delay 60 ps Typical Rise and Fall Times CML Output with Operating Range: VCC = 2.375 V to 3.6 V with VEE = 0 V CML Output Level (400 mV Peak-to-Peak Output), Differential Output Only 50 W Internal Input and Output Termination Resistors Functionally Compatible with Existing 2.5 V / 3.3 V LVEL, LVEP, EP, and SG Devices Pb-Free Packages are Available
Figure 1. Functional Block Diagram
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 11 of this data sheet.
(c) Semiconductor Components Industries, LLC, 2006
February, 2006 - Rev. 1
1
Publication Order Number: NB4L16M/D
NB4L16M
VCC 16 VTD D D VTD 1 2 NB4L16M 3 4 5 VCC 6 NC 7 VEE 8 VEE VBB VEE VEE 15 14 13 12 VCC 11 Q 10 Q 9 VCC Exposed Pad (EP)
Figure 2. Pin Configuration (Top View)
Table 1. PIN DESCRIPTION
Pin 1 2 3 4 15 6 10 11 7, 8, 13, 14 5, 9, 12, 16 - Name VTD D D VTD VBB NC Q Q VEE VCC EP CML Output CML Output - - - I/O - LVPECL, CML, HSTL, LVCMOS, LVDS, LVTTL Input LVPECL, CML, HSTL, LVCMOS, LVDS, LVTTL Input - - Description Internal 50 W termination pin. See Table 4 (Note 1). Inverted differential input. Internal 36.5 kW to VCC and 73 kW to VEE (Note 1). Noninverted differential input. Internal 73 kW to VCC and 36.5 kW to VEE (Note 1). Internal 50 W termination pin. See Table 4. (Note 1) Internally generated reference voltage supply. No Connect pin. The No Connect (NC) pin is electrically connected to the die and MUST be left open. Noninverted differential output. Typically receiver terminated with 50 W resistor to VCC. Inverted differential output. Typically receiver terminated with 50 W resistor to VCC. Negative supply voltage Positive supply voltage Exposed pad (EP). EP on the package bottom is thermally connected to the die for improved heat transfer out of the package. The pad is not electrically connected to the die, but is recommended to be soldered to VEE on the PC Board.
1. In the differential configuration when the input termination pins (VTD, VTD) are connected to a common termination voltage and if no signal is applied on D/D input then the device will be susceptible to self-oscillation.
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Table 2. ATTRIBUTES
Characteristics Input Default State Resistors ESD Protection R1 R2 Human Body Model Machine Model Charged Device Model Pb Pkg QFN-16 Flammability Rating Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 2. For additional information, see Application Note AND8003/D. Oxygen Index: 28 to 34 Level 1 Value 37.5 kW 73 kW > 2 kV > 200 V > 1 kV Pb-Free Pkg Level 1
Moisture Sensitivity (Note 2)
UL 94 V-0 @ 0.125 in 157
Table 3. MAXIMUM RATINGS
Symbol VCC VEE VI VINPP IIN IOUT IBB TA Tstg qJA qJC Tsol Parameter Positive Power Supply Negative Power Supply Positive Input Negative Input Differential Input Voltage Input Current Through RT (50 W Resistor) Output Current VBB Sink/Source Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction-to-Ambient) (Note 3) Thermal Resistance (Junction-to-Case) Wave Solder Pb Pb-Free 0 lfpm 500 lfpm 1S2P (Note 3) QFN-16 QFN-16 QFN-16 Condition 1 VEE = 0 V VCC = 0 V VEE = 0 V VCC = 0 V |D - D| Static Surge Continuous Surge VI = VCC VI = VEE Condition 2 Rating 6 -6 6 -6 |VCC - VEE| 45 80 25 50 0.5 -40 to +85 -65 to +150 42 35 4 265 265 Unit V V V V V mA mA mA mA mA C C C/W C/W C/W C
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 3. JEDEC standard multilayer board - 1S2P (1 signal, 2 power) with 8 filled thermal vias under exposed pad.
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Table 4. DC CHARACTERISTICS, CLOCK INPUTS, CML OUTPUTS VCC = 2.375 V to 3.8 V, VEE = 0 V, TA = -40C to +85C
Symbol ICC VOH VOL VTH VIH VIL VBB VIHD VILD VCMR VID IIH IIL RTIN RTOUT RTemp
Coef
Characteristic Power Supply Current (Inputs and Outputs Open) Output HIGH Voltage (Note 4) Output LOW Voltage (Note 4)
Min 30 VCC - 40 VCC - 500 1050 Vth + 150 VEE VCC - 1500 1200 VEE 1125 150 D D D D 0 0 -100 -150 40 40
Typ 45 VCC - 10 VCC - 400
Max 55 VCC VCC - 300 VCC - 150 VCC Vth - 150
Unit mA mV mV
DIFFERENTIAL INPUT DRIVEN SINGLE-ENDED (Figures 15 and 17) Input Threshold Reference Voltage Range (Note 6) Single-ended Input HIGH Voltage Single-ended Input LOW Voltage Internally Generated Reference Voltage Supply (Loaded with -100 mA) Differential Input HIGH Voltage Differential Input LOW Voltage Input Common Mode Range (Differential Configuration) Differential Input Voltage (VIHD - VILD) Input HIGH Current (VTD/VTD Open) Input LOW Current (VTD/VTD Open) Internal Input Termination Resistor Internal Output Termination Resistor Internal I/O Termination Resistor Temperature Coefficient mV mV mV mV
VCC - 1400
VCC - 1300 VCC VCC - 150 VCC - 75 VCC - VEE
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (Figures 16 and 18) mV mV mV mV mA mA W W mW/C
100 50 -50 -100 50 50 16
150 100 0 0 60 60
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 4. CML outputs require 50 W receiver termination resistors to VCC for proper operation. See Figure 14. 5. Input and output parameters vary 1:1 with VCC. 6. Vth is applied to the complementary input when operating in single-ended mode. 7. VCMR min varies 1:1 with VEE, VCMRmax varies 1:1 with VCC. The VCMR range is referenced to the most positive side of the differential input signal.
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NB4L16M
Table 5. AC CHARACTERISTICS VCC = 2.375 V to 3.8 V, VEE = 0 V; (Note 8)
-40C Symbol VOUTPP fDATA tPLH, tPHL tSKEW tJITTER Characteristic Output Voltage Amplitude (@VINPPmin) fin 3.5 GHz (Figures 3 and 4) fin 4.5 GHz Maximum Operating Data Rate Propagation Delay to Output Differential @ 0.5 GHz (Figure 6) Duty Cycle Skew (Note 9) Device-to-Device Skew (Note 13) RMS Random Clock Jitter (Note 11) fin 4.5 GHz Min 280 150 3.5 175 Typ 400 300 5.0 215 2.0 6.0 0.2 1.5 2.0 9.0 75 60 265 10 90 0.7 10 12 25 VCC -VEE 90 75 60 Max Min 280 150 3.5 175 25C Typ 400 300 5.0 220 2.0 6.0 0.2 1.5 2.0 9.0 265 10 90 0.7 10 12 25 VCC -VEE 90 75 Max Min 280 150 3.5 175 85C Typ 400 300 5.0 225 2.0 6.0 0.2 1.5 2.0 9.0 VCC -VEE 60 90 265 10 90 0.7 10 12 25 mV ps Max Unit mV Gb/s ps ps ps
Peak-to-Peak Data Dependent Jitter (Note 12) fDATA = 2.5 Gb/s fDATA = 3.5 Gb/s fDATA = 5.0 Gb/s VINPP tr tf Input Voltage Swing/Sensitivity (Differential Configuration) (Note 10) Output Rise/Fall Times @ 0.5 GHz (Figure 5) (20% - 80%)
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 8. Measured by forcing VINPP(MIN) from a 50% duty cycle clock source. All loading with an external RL = 50 W to VCC. Input edge rates 40 ps (20% - 80%). See Figure 12 and 14. 9. Duty cycle skew is measured between differential outputs using the deviations of the sum of Tpw- and Tpw+ @ 0.5 GHz. 10. VINPP(MAX) cannot exceed VCC - VEE. Input voltage swing is a single-ended measurement operating in differential mode. See Figure 11. 11. Additive RMS jitter with 50% duty cycle input clock signal. 12. Additive peak-to-peak data dependent jitter with NRZ input data signal, PRBS 223-1 and K28.7 pattern. See Figures 7, 8, 9, 10, 11 and 12. 13. Device-to-device skew is measured between outputs under identical transition @ 0.5 GHz.
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NB4L16M
TYPICAL OPERATING CHARACTERISTICS
OUTPUT VOLTAGE AMPLITUDE (mV)
400 350 300 250 200 150 100 50 0 0 2 2.5 3 3.5 4 4.5 5 5.5 INPUT CLOCK FREQUENCY (GHz) +85C +25C -40C
OUTPUT VOLTAGE AMPLITUDE (mV)
450
450 400 350 300 250 200 150 100 50 0 0 2 2.5 3 3.5 4 4.5 5 5.5 INPUT CLOCK FREQUENCY (GHz) +25C +85C -40C
Figure 3. Output Voltage Amplitude (VOUTPP) vs. Input Clock Frequency (fin) and Temperature at 3.3 V Power Supply
Figure 4. Output Voltage Amplitude (VOUTPP) vs Input Clock Frequency (fin) and Temperature at 2.5 V Power Supply
90 80 70 TIME (ps) TIME (ps) VCC = 3.3 V 60 50 40 30 -40 VCC = 2.5 V
265 255 245 235 225 215 205 195 185 25 TEMPERATURE (C) 85 175 -40 25 TEMPERATURE (C) 85 VCC = 2.5 V VCC = 3.3 V
Figure 5. Rise/Fall Time vs Temperature and Power Supply
Figure 6. Propagation Delay vs Temperature and Power Supply
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NB4L16M
VOLTAGE (50 mV/div)
VOLTAGE (50 mV/div)
Device DDJ = 1.5 ps
Device DDJ = 2 ps
TIME (80 ps/div)
TIME (60 ps/div)
Figure 7. Typical Output Waveform at 2.488 Gb/s with PRBS 223-1 (VINPP = 75 mV; Input Signal DDJ = 12 ps)
Figure 8. Typical Output Waveform at 3.2 Gb/s with PRBS 2^23-1 (VINPP = 75 mV; Input Signal DDJ = 12 ps)
VOLTAGE (64 mV/div)
Device DDJ = 1.5 ps
VOLTAGE (64 mV/div)
Device DDJ = 2 ps
TIME (72 ps/div)
TIME (60 ps/div)
Figure 9. Typical Output Waveform at 2.488 Gb/s with PRBS 223-1 (VINPP = 400 mV; Input Signal DDJ = 12 ps)
Figure 10. Typical Output Waveform at 3.2 Gb/s with PRBS 223-1 (VINPP = 400 mV; Input Signal DDJ = 12 ps)
VOLTAGE (64 mV/div)
Device DDJ = 9 ps
VOLTAGE (64 mV/div)
Device DDJ = 14 ps
TIME (43 ps/div)
TIME (36 ps/div)
Figure 11. Typical Output Waveform at 5 Gb/s with PRBS 223-1 (VINPP = 400 mV; Input Signal DDJ = 13 ps)
Figure 12. Typical Output Waveform at 6.125 Gb/s with PRBS 223-1 (VINPP = 400 mV; Input Signal DDJ = 15 ps)
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NB4L16M
D VINPP = VIH(D) - VIL(D) D Q VOUTPP = VOH(Q) - VOL(Q) Q tPHL tPLH
Figure 13. AC Reference Measurement
VCC
50 W Q Driver Device Q Zo = 50 W Zo = 50 W
50 W D Receiver Device D
Figure 14. Typical Termination for Output Driver and Device Evaluation
D Vth
D
D Vth
D
Figure 15. Differential Input Driven Single-Ended
Figure 16. Differential Inputs Driven Differentially
VCC Vthmax
VIHmax VILmax VIH Vth VIL VIHmin VILmin
VCC VCMmax
VIHDmax VILDmax VIHDtyp VILDtyp VID = VIHD - VILD
Vth Vthmin GND
VCMR
VCMmax GND
VIHDmin VILDmin
Figure 17. Vth Diagram
NOTE: VEE v VIN v VCC; VIH > VIL
Figure 18. VCMR Diagram
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NB4L16M
VCC
50 W
50 W Q Q
16 mA
VEE
Figure 19. CML Output Structure
Table 6. INTERFACING OPTIONS
INTERFACING OPTIONS CML LVDS AC-COUPLED RSECL, PECL, NECL LVTTL, LVCMOS Connect VTD and VTD to VCC Connect VTD and VTD Together Bias VTD and VTD Inputs within Common Mode Range (VCMR) Standard ECL Termination Techniques An External Voltage (VTHR) should be applied to the unused complementary differential input. Nominal VTHR is 1.5 V for LVTTL and VCC/2 for LVCMOS inputs. This voltage must be within the VTHR specification. CONNECTIONS
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NB4L16M
Application Information All NB4L16M inputs can accept LVPECL, CML, LVTTL, LVCMOS and LVDS signal levels. The limitations for differential input signal (LVDS, PECL, or CML) are minimum input swing of 75 mV and the maximum input swing of 2500 mV. Within these conditions, the input voltage can range from VCC to 1.2 V. Examples interfaces are illustrated below in a 50 W environment (Z = 50 W).
VCC VCC
50 W
50 W
Q
Z VCC VCC Z
D VTD VTD D VEE 50 W
50 W
Q VEE
Figure 20. CML to CML Interface
VCC VCC
50 W PECL Driver Recommended RT Values VCC RT VEE 5.0 V 290 W 3.3 V 150 W 2.5 V 80 W RT VEE 50 W RT
Z VBIAS VBIAS Z
D VTD VTD D VEE 50 W
50 W
Figure 21. PECL to CML Receiver Interface
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NB4L16M
VCC VCC
LVDS Driver
Z
D VTD VTD 50 W 50 W
Z D VEE VEE
Figure 22. LVDS to CML Receiver Interface
VCC
VCC
Z LVTTL/ LVCMOS Driver No Connect No Connect VREF
D 50 W VTD VTD 50 W D VCC Recommended VREF Values VREF LVCMOS VCC * VEE 2 LVTTL 1.5 V
VEE
Figure 23. LVCMOS/LVTTL to CML Receiver Interface
ORDERING INFORMATION
Device NB4L16MMN NB4L16MMNG NB4L16MMNR2 NB4L16MMNR2G Package QFN-16 QFN-16 (Pb-Free) QFN-16 QFN-16 (Pb-Free) Shipping 123 Units / Rail 123 Units / Rail 3000 / Tape & Reel 3000 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
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NB4L16M
PACKAGE DIMENSIONS
16 PIN QFN CASE 485G-01 ISSUE B
D A B
NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. 5. Lmax CONDITION CAN NOT VIOLATE 0.2 MM MINIMUM SPACING BETWEEN LEAD TIP AND FLAG DIM A A1 A3 b D D2 E E2 e K L SEATING PLANE MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.18 0.30 3.00 BSC 1.65 1.85 3.00 BSC 1.65 1.85 0.50 BSC 0.20 --- 0.30 0.50
PIN 1 LOCATION
0.15 C 0.15 C 0.10 C
16 X
0.08 C
16X
L
NOTE 5 4
16X
K
1 16 16X 13
0.10 C A B 0.05 C
NOTE 3
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT: N. American Technical Support: 800-282-9855 Toll Free Literature Distribution Center for ON Semiconductor USA/Canada P.O. Box 61312, Phoenix, Arizona 85082-1312 USA Phone: 480-829-7710 or 800-344-3860 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 2-9-1 Kamimeguro, Meguro-ku, Tokyo, Japan 153-0051 Fax: 480-829-7709 or 800-344-3867 Toll Free USA/Canada Phone: 81-3-5773-3850 Email: orderlit@onsemi.com ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative.
CCC CCC
TOP VIEW SIDE VIEW D2
5
E
(A3) A A1
C
SOLDERING FOOTPRINT*
3.25 0.128 0.30 0.012
e
8
EXPOSED PAD
0.575 0.022
EXPOSED PAD
9
E2
12
e
3.25 0.128
1.50 0.059
b BOTTOM VIEW 0.50 0.02
0.30 0.012
SCALE 10:1 mm inches
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
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NB4L16M/D

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